The present invention relates to a semiconductor storage circuit and an operation method thereof and particularly to an operation method of a semiconductor storage circuit having an error checking and correction (ECC) function.
The ECC function that detects and corrects an error in stored data is widely used as a technique for enhancing data reliability of a semiconductor storage circuit. Recently, not only an independent memory chip, also a memory macro integrated into an LSI with embedded memory may be equipped with the ECC function.
A memory macro equipped with the ECC function is disclosed in, e.g., Japanese Unexamined Patent Application Publication No. 2010-086120. FIG. 1 presents a configuration of a controller 16 disclosed in this publication. The controller 106 includes a memory 101, a memory controller 102, and a processor 104. The memory 101 and the memory controller 102 are connected by a set of signal lines 103. The memory controller 102 and the processor 104 are connected by a set of signal lines 105. When the processor 104 commands the memory controller 102 to initiate a read or write operation by control signals (clock CLK, read/write control RW, transfer start BS, and address and data AD) which are transmitted through the set of signal lines 105, the memory controller 102 gets access to the memory 101 (and executes the read or write operation) by control signals (clock CLK, address A, row address strobe RAS, column address strobe CAS, write enable WE, data mask DM, data strobe DQS, and data DQ) which are transmitted through the set of signal lines 103. The memory controller 102 has the ECC function and performs ECC encoding and ECC decoding.
Other memory macros equipped with the ECC function are disclosed in Japanese Unexamined Patent Application Publications No. 2002-74983, No. 2006-244632, and No. 2008-90419.
One requirement imposed on a semiconductor storage device is to increase its operating frequency for read and write operations. By increasing the operating frequency, read and write operations at a higher speed can be achieved.
Another requirement is to maintain complete random accessibility in each operation cycle including switching between a read operation and a write operation. For example, a situation in which a read operation is prohibited in an operation cycle following a cycle of a write operation commanded complicates a control logic that is used for externally controlling the semiconductor storage circuit and results in a decrease in the random accessibility.
However, the addition of the ECC function may make it impossible to satisfy the foregoing requirements together. For example, a higher operating frequency, if applied, may make it impossible to complete ECC encoding and writing into a memory cell in one operation cycle and, similarly, may make it impossible to complete reading from a memory cell and ECC decoding in one operation cycle. Under a condition that ECC processing (that is, ECC encoding or ECC decoding) and access to a memory cell should be completed in a single operation cycle, the operating frequency is restricted to a frequency that is consistent with the sum of a time taken for the ECC processing and a time taken for the access to the memory cell.
One method for coping with such a problem is pipelining of processing for memory access and ECC encoding or ECC decoding, as disclosed in, e.g., Japanese Unexamined Patent Application Publication No. 2010-086120 mentioned above. That is, for a write operation, ECC encoding is performed in an operation cycle beginning with the input of a write command, data, and an address, and the data is written into a memory core in the next operation cycle. For a read operation, data is read from the memory core in an operation cycle beginning with the input of a read command and an address, and ECC decoding is performed in the next operation cycle. In this way of operation, the length of one operation cycle can be shortened and, thus, ECC processing can be performed without a decrease in the operating frequency.
FIG. 2 is a timing chart presenting an example of a write operation and a read operation of the semiconductor storage circuit of FIG. 1. An operation sequence in which ECC processing and memory access are pipelined, as noted above, is illustrated in FIG. 2. Here, note the following. The memory controller 102 in the circuit of FIG. 1 is configured to transfer an address received from the processor 104 directly to the memory 101 and, at the same time, perform ECC processing. In consequence, operations are to take place such that ECC encoding is performed in an operation cycle beginning with the input of a write command, data, and an address, and the data is written into the memory core in the next operation cycle.
In the operation sequence of FIG. 2, for example, at a time instant t1, when a write command is input, an address signal specifying an address A1 is input, and data D1 is input to a data input, ECC processing is performed in an operation cycle starting from the time instant t1. In the next operation cycle (starting at a time instant t2), the memory 101 is activated and writing of the data is performed. At a time instant t3, when a read command is input and an address signal specifying an address A2 is input, the memory 101 is activated and reading of data is performed in an operation cycle starting from the time instant t3. In the next operation cycle (starting at a time instant t4), ECC decoding is performed.
However, in the operation sequence illustrated in FIG. 2, the number of write cycles (the number of operation cycles required to complete data writing after the input of a write command) degrades to 2. The number of read cycles (the number of operation cycles required to complete data reading after the input of a read command) also degrades to 2.
In addition, in the operation sequence illustrated in FIG. 2, it is necessary to prohibit input of a read command in an operation cycle following the cycle beginning with the input of a write command and random accessibility is lost. Access to the memory 101 for a writing operation takes place in an operation cycle following the operation cycle beginning with the input of a write command, whereas access to the memory 101 for a read operation takes place in an operation cycle beginning with the input of a read command. Hence, if a read command is input in the operation cycle following the cycle beginning with the input of a write command, collision of access to the memory 101 would occur.
In order to resolve such a trouble, it is conceivable that access to the memory 101 is made to take place in an operation cycle following the operation cycle beginning with the input of a read command, thus avoiding access collision. However, in such an operation sequence, the number of read cycles increases to 3.
Such a problem becomes an issue particularly for an LSI with embedded memory. Because a memory interface is not a bottleneck for an LSI with embedded memory, the operating speed of a memory core is increased and, besides, there is a large requirement for random access performance. Therefore, the problem of an increase in the number of cycles required for a write operation and a read operation and the problem of restriction of input timing of a write command and a read command become particularly serious.